1. Field of the Invention
The present invention relates to semiconductor devices carrying out data output in synchronization with an external clock signal, more particularly, to a semiconductor device including a clock generation circuit generating an internal clock signal in synchronization with an external clock signal.
2. Description of the Background Art
Data transmission in a semiconductor device is executed by an output circuit in a semiconductor device driving a transmission line to transmit data to the receiving end. As an example of transmitting data with a semiconductor device connected to a transmission line whose one end is an open end, a transient phenomenon thereof will be described briefly hereinafter.
A transmission line connected to an output circuit has a characteristic impedance of 50 xcexa9 in an ideal situation. The transmission line has one end connected to the output circuit whereas the other end is an open end (impedance corresponding to infinity). The data signal from the output circuit travels the transmission line as a signal wave of a voltage level corresponding to the resistance division ratio of the output impedance of the output circuit to the characteristic impedance of the transmission line at the connection end. At the receiving end of the transmission line that is an open end, the signal wave is totally reflected. A signal wave of two times the voltage is observed. The reflected signal wave returns to the connection end, and the reflected wave that is resistance-divided proceeds towards the receiving end.
When the output impedance of the output circuit matches the characteristic impedance of the transmission line in the above data transmission flow, i.e., when the output impedance is equal to the characteristic impedance, there will be no signal reflection at the connection end. No attenuation in the signal wave through the transmission line will occur.
In the case where the output impedance does not match the characteristic impedance, for example when the output impedance is lower than the characteristic impedance, the drivability of the transmission line will be excessive at the receiving end, resulting in overshooting/undershooting. When the output impedance is higher than the characteristic impedance, the drivability will be insufficient. The voltage level at the receiving end will become closer to the stable point in a stepped manner.
Since data transmission greatly depends on the output impedance, various devices for impedance matching has been provided in conventional LSIs (Large Scale Integrated Circuit). Recently, LSIs capable of impedance matching are proposed, taking into account impedance variation caused by change in the usage environment such as the fabrication process, used temperature, power supply voltage and the like as disclosed in, for example, Japanese Patent Laying-Open No. 2001-217705.
In such impedance matching, the output impedance must match even between the pull up and pull down of the output circuit. This is because mismatch in impedance between the pull up side and the pull down side of the output circuit will cause difference in the transition time of the rise and fall of the signal even if the individual impedance approximates each other at the pull up side and the pull down side. This difference in the transition time will adversely affect data transfer.
During data transfer in an LSI, high speed data transmission is required in addition to the above impedance matching. To this end, an internal clock signal generated by a clock generation circuit in synchronization with an external clock signal is used for control.
In a data transmission operation in synchronization with the external clock signal, deviation will occur although data output is in synchronization with the external clock signal if the external clock signal is first received at the LSI and data is then output from the LSI. There is a problem that determination of which clock transition the output data establishes synchronization with cannot be made at the receiver side.
Recently, LSIs include a DLL (Delay Locked Loop) circuit to generate an internal clock signal in synchronization with an external clock signal to keep the transition time position properly in phase with the external clock signal, whereby data transmission/reception is conducted by an internal clock signal that is completely in synchronization with the external clock signal. The DLL circuit delays the external clock signal internally in a fixed and variable manner to generate an internal clock signal for data output that is ahead in phase of the external clock signal.
By adjusting the phase of the internal clock signal for data output taking into consideration the delay in the clock input buffer that buffers the external clock signal and the data output buffer corresponding to the above-described output circuit, the phase of the external clock signal is set to match the phase of the data output. Therefore, an input replica circuit and an output replica circuit are provided as a replica delay circuit to compensate for the delay of the clock input buffer and data output buffer in the DLL circuit.
If the above-described impedance matching is established only for the output circuit and not for the output replica circuit in a semiconductor device with a DLL circuit, the output replica circuit cannot properly compensate for the delay of the output circuit. There is a possibility that the phase of the external clock signal will deviate from the matching state with the phase of the data output. Accordingly, proper data transmission in synchronization with an external clock signal in a semiconductor device will be inhibited.
An object of the present invention is to provide a semiconductor device with a clock generation circuit, capable of data transmission constantly in synchronization with an external clock signal at high speed before and after output impedance adjustment.
According to an aspect of the present invention, a semiconductor device operating in synchronization with an external clock signal includes a clock generation circuit generating an internal clock signal in synchronization with an external clock signal, an output circuit providing a data signal outside the semiconductor device in response to the internal clock signal, and an impedance adjustment circuit generating an impedance adjustment signal to adjust the output impedance of the output circuit. The clock generation circuit includes a replica delay circuit to delay the internal clock signal for a predetermined time corresponding to the predetermined time of a data signal output operation in the output circuit. The impedance adjustment circuit applies the impedance adjustment signal to the output circuit as well as to the replica delay circuit.
According to the present invention, by applying the impedance adjustment signal input to the output circuit also to an output replica circuit in the DLL circuit at the same time, the impedance of the output replica circuit is also adjusted following adjustment of the impedance of the output circuit. Therefore, the DLL circuit can constantly compensate for the delay in the output circuit to allow data transmission properly in synchronization with an external clock signal in an LSI.